Since the binary counter is one of the most useful of logical circuits, there are many kinds of binary counters. As is well known, the fundamental purpose of the binary counter is to record the number of occurrences of some input.
In an asynchronous binary counter comprising an array of flip-flops, an input signal is frequency divided while advancing down the counter. As a consequence, the flip-flops indicating upper bits may be of slow response type as against those indicating the lower bits. This is advantageous where the counter is constructed of MOS FETs (Metal-oxide semiconductor Field-effect transistors) in that a MOS FET flip-flop of slow response type can be manufactured in smaller size on a silicon chip without adversely affecting its response reliability. Hence such a counter can be reduced in size and this is markedly advantageous where the counter includes a large number of flip-flops.
However, if the counter is programmable and includes a large number of flip-flops to be preset by a pulse with a narrow width, the above advantage can not be realized. This is because even the flip-flops indicating the upper bits should be so fabricated as to reliably respond to such a narrow preset pulse. This case would arise if one of high frequency input pulses is used as a preset pulse.
Therefore, in order to overcome this difficulty, there has been proposed an improvement as shown in FIG. 2 of the accompanying drawings.
Prior to a description of this invention, the conventional programmable, asynchronous binary down counter of FIG. 1 will be discussed with reference to FIG. 3.
As shown in FIG. 1, a plurality of T type flip-flops 2(1)-2(N) are coupled in cascade. Before counting starts, the desired number of the flip-flops are preset to logic 1 while the remaining are preset to logic 0, by applying appropriate preset signals to them through a preset terminal 5 and data input terminals 6(1)-6(N), respectively. These terminals 5 and 6(1)-6(N) are coupled to suitable gates, although not shown. It is here assumed for convenience that all the flip-flops 2(1)-2(N) are preset to logic 1. At this time, the initial logic states of the counter are as shown in the second line of FIG. 3 (i.e., 111111 . . . 11 (binary code)=x (decimal digit)). When a first input pulse is applied to the counter through an input terminal 8, the flip-flop 2(1) goes to logic 0 in response to the input pulse. The other flip-flops 2(2)-2(N) are not affected by this change, thus, the logic states of all the flip-flops are as shown in the third line of FIG. 3 (i.e., 011111 . . . 11). The occurrence of the second input pulse causes the flip-flop 2(1) to go from logic 0 to 1, and substantially at the same time causing the flip-flop 2(2) to go from logic 1 to 0. Therefore, the logic states of the counter becomes as shown in the fourth line of FIG. 3 (i.e., 101111 . . . 11). Thus, the counter counts down from the preset binary digit, and when reaching 111100 . . . 00 (decimal 15), each of the flip-flops 2(5)-2(N) assumes a logic 0. Hence, an OR gate 10 changes its output level from logic 1 to 0. At this time, however, all input lines of a NOR gate 14 are not at logic 0's so that the gate 14 remains at logic 0. Thereafter, when the counter counts down to 010000 . . . 00 (decimal 2), the NOR gate 14 assumes a logic 1 in that (1) an inverter 12 is interposed between the flip-flop 2(2) and the gate 14, and (2) the gate 10 remains at the logic 0 at this time. As a result, a D type flip-flop 16 assumes a logic 1 in response to a logic 1 of the input signal applied through the terminal 8. The logic 1 state of the D type flip-flop 16 causes all the flip-flops 2(1)-2(N) to be preset to the initial logic states for the next counting cycle, through a preset line 4. The output of the counter is derived from an output terminal 17 if desired every counting cycle. Alternatively, if the output of the counter is needed every input cycle, the logic states of all the flip-flops should be derived by providing each flip-flop with an additional output.
It is understood that the pulse width of the preset signal is about two times that of the input pulse applied to the T input. Resultantly, according to this prior art, some flip-flops indicating upper bits can be somewhat reduced in size as opposed to the case where the flip-flop 16 is not provided.
However, if the counter of FIG. 1 includes a large number of flip-flops and should count in response to a high frequency input signal, then the width of the preset pulse is insufficient for reliable presetting, thereby making it impossible to reduce the counter size. More specifically, assuming that the number of the flip-flops is 10 and the repetition frequency of the input is 8 MHz (a pulse width 250 ns), the tenth or rightmost flip-flop receives a toggling pulse with a width of 16 .mu.s from its preceding flip-flop. Whilst, the tenth flip-flop receives a preset pulse width of 500 ns. Therefore, the tenth flip-flop must be manufactured so as to reliably respond to the preset pulse (500 ns) not to the toggling pulse (16 .mu.s). This also applies to the other flip-flops indicating upper bits.
It is therefore a primary object of this invention to provide a programmable, asynchronous binary down counter having a small size while maintaining a reliable response to a high frequency input.
Another object of this invention is to provide a miniaturized programmable, asynchronous binary down counter constructed on a silicon chip by using MOS technology without adversely affecting the reliability of response to a high frequency input.
Still another object of this invention is to provide a programmable, asynchronous binary down counter including a plurality of flip-flops which are divided into two groups for effectively presetting.